Error Control: The device controller also manages error detection of data transmitted from the I/O device. If it is found that an error has occurred in the transmission, the error detection code is usually set and reported to the CPU. The CPU then invalidates the data transmitted this time and retransmits the data again. This will ensure correct data entry.
Data Exchange: This refers to the exchange of data between the CPU and the controller and between the controller and the device. For the former, data is written to the controller in parallel by the CPU through the data bus, or read out from the controller in parallel; for the latter, the device inputs data to the controller or from the controller to the device. . To do this, set the data register in the controller.
State Description: The status controller that identifies and reports the device should note the status of the device for the CPU to understand. For example, the CPU can start the controller to read data from the device only when the device is in a ready-to-send state. To this end, a status register should be set in the controller, with each of these bits reflecting a certain state of the device. When the CPU reads the contents of the register, it can understand the status of the device.
Receive and identify commands: The CPU can send a variety of different commands to the controller. The device controller should be able to receive and recognize these commands. For this purpose, a corresponding control register should be provided in the controller for storing the received command and parameters and decoding the received command. For example, the disk controller can receive 15 different commands such as Read, Write, Format, etc. sent by the CPU, and some commands also have parameters; accordingly, there are multiple registers and command decoders in the disk controller.
Address identification: Just as every unit in the memory has an address, every device in the system has an address, and the device controller must be able to identify the address of each device it controls. In addition, these registers should have unique addresses in order for the CPU to write (or read) data into (or from) registers.
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